SD (Standard Definition)-SDI and HD (High Definition)-SDI are known as SDI standards. A signal transmission standard known as 3G-SDI having twice the transmission speed as HD-SDI has also been recently introduced.
As shown in FIG. 1, the SD-SDI and HD-SDI standards deal with YCbCr 10-bit parallel data, and the frequency of the parallel clock for achieving synchronization of parallel data is 27 MHz for SD-SDI and 148.5 MHz for HD-SDI. The frequency of the pixel clock (sampling rate) is 13.5 MHz for SD-SDI and 74.25 MHz for HD-SDI.
On the other hand, the 3G-SDI standard deals with 10-bit or 12-bit RGB or YCbCr parallel data, the frequency of the clock (transmission clock) for achieving synchronization of the parallel data is 297 MHz, and the frequency of the pixel clock is 74.25 MHz or 148.5 MHz.
As can be understood from the foregoing explanation, the video format and color mapping based on the 3G-SDI standard differs from its counterparts that are based on the SD-SDI or HD-SDI standards. In addition, the frequencies of the parallel clocks of each of SD-SDI, HD-SDI, and 3G-SDI also differ. As a result, in order to process data of the each of the SD-SDI, HD-SDI, and 3G-SDI standards, a video processing device that processes SDI signals must implement both conversion to multiple rates as well as processing that corresponds to the formats (video formats and color mapping) of each of the standards.
FIG. 2 shows the configuration of a video apparatus that is equipped with a multi-rate video processing device that corresponds to each of the SD-SDI, HD-SDI, and 3G-SDI standards.
Referring to FIG. 2, the video processing device includes: deserializer 100, descrambler 101, timing signal extraction/signal format detection circuit 102, Y/C channel separation circuit 103, link separation circuit 104, UNPACK circuits 105-107, selectors 108 and 109, and frequency-dividing circuit 110. A video apparatus is realized by adding image adjustment circuit 111 and video display apparatus 112 to this video processing device.
Deserializer 100 includes an SDI input terminal, a clock output terminal, and a data output terminal.
SDI signals of any of the SD-SDI, HD-SDI, and 3G-SDI standards that are supplied from an SDI-compatible outside transmission device are supplied to the SDI input terminal of deserializer 100.
The outside transmission device is here briefly described.
The outside transmission device includes a signal processor, a serializer, and a transmission unit.
The signal processor takes as input each data item that includes video data or supplementary data (such as audio data), a parallel clock, and a timing signal, implements various processes such as scrambling input data, inserting a timing signal, or pack processing, and based on the parallel clock, generates parallel data based on the data that follows this processing. The signal processor supplies parallel data and a parallel clock to the serializer.
The serializer generates a serial clock based on the parallel clock that was received as input, and based on this generated serial clock, converts parallel data received as input to serial data.
The transmission unit supplies the serial data (SDI signals) that are supplied from the serializer by way of coaxial cable to the SDI input terminal of deserializer 100.
Scrambled NRZI (Non Return to Zero Inverted) is typically used as the coding to accurately transmit information of clocks. NRZI coding is a coding scheme that continues the signal level when “0” is transmitted and inverts the immediately preceding signal level when “1” is transmitted.
Referring again to FIG. 2, deserializer 100 converts SDI signals that are applied as input to the SDI input terminal to 10-bit parallel data, and supplies this parallel data from the data output terminal. Deserializer 100 further extracts information of the parallel clock and supplies the extracted parallel clock from the clock output terminal.
Although not shown in FIG. 2, the clock that is supplied from the clock output terminal is supplied to each of timing signal extraction/signal format detection circuit 102, Y/C channel separation circuit 103; link separation circuit 104, UNPACK circuits 105-107, frequency-dividing circuit 110, and image adjustment circuit 111; and each circuit operates based on the supplied clock.
Descrambler 101 has a data input terminal and a data output terminal. The parallel signal that is supplied from the data output terminal of deserializer 100 is supplied to the data input terminal of descrambler 101.
Descrambler 101 restores parallel data that are applied as input to the data input terminal to the original data. Here, this original data is the parallel data that precedes the scrambled NRZI process in the above-described outside transmission device. Descrambler 101 supplies this restored data from the data output terminal.
Timing signal extraction/signal format detection circuit 102 has a data input terminal and a format output terminal. Y/C channel separation circuit 103 has a data input terminal, a Y/C output terminal, and a CE output terminal.
Restored data that are supplied from the data output terminal of descrambler 101 are supplied to the data input terminals of each of timing signal extraction/signal format detection circuit 102 and Y/C channel separation circuit 103.
Timing signal extraction/signal format detection circuit 102 both extracts a timing signal from the restored data that are applied as input to the data input terminal and specifies the starting positions of frames of the restored data based on the result of extraction of the timing signal Timing signal extraction/signal format detection circuit 102 then refers to the starting positions of the frames that were specified to detect the signal format (the format that conforms to the SDI standard) of the restored data and supplies the detection result from the format output terminal.
Y/C channel separation circuit 103 separates the restored data that are received as input into a 10-bit Y-channel and a 10-bit C-channel.
When the restored data input is SD-SDI, Y/C channel separation circuit 103 supplies the Y-channel signal and the C-channel signal to the Y/C input terminal of SD-SDI UNPACK circuit 105.
When the restored data input is HD-SDI, Y/C channel separation circuit 103 supplies the Y-channel signal and C-channel signal to the input terminal IN1 of selector 109.
Due to the difference in multiplex methods in the 3G-SDI standard, there are two mapping schemes, level A and level B. Level A and level B can be distinguished by this difference in mapping.
When the restored data input is data of level A of 3G-SDI, Y/C channel separation circuit 103 supplies the Y-channel signal and C-channel signal to UNPACK circuit 106. When the restored data input is data of level B of 3G-SDI, Y/C channel separation circuit 103 supplies the Y-channel signal and C-channel signal to link separation circuit 104.
In addition, Y/C channel separation circuit 103 synchronizes with the clock signal from deserializer 100 to supply a Clock Enable from CE output terminal. Clock Enable causes processing in each circuit to be executed at a period that matches the video data and has a frequency of one-half that of the input clock signal. Clock Enable is supplied to each of input terminal in1 of selector 108, terminal CEin of link separation circuit 104, and terminal CEin of UNPACK circuit 106.
UNPACK circuit 106 carries out a process of unpacking the Y-channel signal and C-channel signal of the level-A mapping to acquire a video signal. The video signal is supplied to input terminal In2 of selector 109 from the data output terminal of UNPACK circuit 106. UNPACK circuit 106 further supplies the Clock Enable that was supplied from terminal CEin from terminal CEout. The Clock Enable that is supplied from terminal CEout is supplied to input terminal In2 of selector 108.
Link separation circuit 104 separates each of the Y-channel signal and C-channel signal of level-B mapping into link A that uses odd-numbered channels and link B that uses even-numbered channels. The data of link-A channels and the data of link-B channels are supplied to Y/C input terminal of UNPACK circuit 107.
Link separation circuit 104 further supplies the Clock Enable that was supplied to terminal CEin from terminal CEout. The Clock Enable that is supplied from terminal CEout is supplied to terminal CEin of UNPACK circuit 107.
UNPACK circuit 107 unpacks the link-A channel data and link-B channel data that are supplied to the Y/C input terminal to acquire video signals.
The video signals are supplied from the data output terminal of UNPACK circuit 107 to input terminal In3 of selector 109. UNPACK circuit 107 further supplies the Clock Enable that was supplied to terminal CEin from terminal CEout. The Clock Enable that is supplied from terminal CEout is supplied to input terminal In3 of selector 108.
In accordance with the format detection results from timing signal extraction/signal format detection circuit 102, selector 108 selects one of input terminals in0-In3 to which the Clock Enable is supplied and supplies the Clock Enable that was supplied to the selected input terminal from the output terminal. More specifically, input terminal In0 is selected when the format detection result is SD-SDI; input terminal In1 is selected when the format detection result is HD-SDI, and input terminal In2 is selected when the format detection result is level A of 3G-SDI. Input terminal In3 is selected when the format detection result is level B of 3G-SDI.
The Clock Enable that was supplied from selector 108 is supplied to frequency-dividing circuit 110 and image adjustment circuit 111.
In accordance with the format detection result from timing signal extraction/signal format detection circuit 102, selector 109 selects one input terminal from among input terminals In0-In3 to which video signals are supplied and supplies the video signal that is supplied to the selected input terminal from the output terminal. More specifically, Input terminal In0 is selected when the format detection result is SD-SDI; input terminal In1 is selected when the format detection result is HD-SDI, input terminal In2 is selected when the format detection result is level A of 3G-SDI, and input terminal In3 is selected when the format detection result is level B of 3G-SDI.
The video signal that is supplied from selector 109 is supplied to image adjustment circuit 111.
Image adjustment circuit 111 subjects the input video signal to processes that are necessary for video display on video display apparatus 112, such as an enlargement or reduction process or a gamma correction process.
Based on the Clock Enable input, frequency-dividing circuit 110 generates a pixel clock that is necessary for video display by video display apparatus 112.
As shown in FIG. 1, the clock frequencies in each of SD-SDI, HD-SDI, and 3G-SDI are different, and moreover, the ratios of clock frequency and pixel clock frequency differ between levels A and B for 3G-SDI.
In the video processing device described hereinabove, Y/C channel separation circuit 103 generates Clock Enable to process video data in which the ratios of clock frequency and pixel clock frequency differ. Based on this Clock Enable, the processing of video data is carried out in each of link separation circuit 104, UNPACK circuits 106 and 107, and image adjustment circuit 111.
When supplying video data to video display apparatus 112, frequency-dividing circuit 110 generates a pixel clock from the Clock Enable. The video data are supplied to video display apparatus 112 together with the pixel clock that was generated in frequency-dividing circuit 110.
The Clock Enable is not supplied to UNPACK circuit 105. UNPACK circuit 105 both carries out processing of video data based on the clock signal from deserializer 100 and supplies the input clock signal as is as the Clock Enable.
FIG. 3 shows a data output circuit that synchronizes with the Clock Enable and supplies data as output. This data output circuit is used in link separation circuit 104, UNPACK circuits 106 and 107, and image adjustment circuit 111.
The data output circuit shown in FIG. 3 includes AND circuit 120 and flip-flop 121. AND circuit 120 is a component that obtains output Y from two inputs A and B, is supplied with Clock Enable as input A, and is supplied with data as input B. Output Y is a value that takes the logical product of inputs A and B.
Flip-flop 121 includes data input terminal D, clock input terminal C, and data output terminal Q. Flip-flop 121 operates based on the clock that is supplied to clock input terminal C and temporarily saves data that is supplied to data input terminal D. Output Y of AND circuit 120 is supplied to data input terminal D of flip-flop 121.
FIG. 4 is a timing chart showing the operation of the data output circuit shown in FIG. 3.
As shown in FIG. 4, video data are supplied to data input terminal D of flip-flop 121 at the intervals of the active state of the Clock Enable. Flip-flop 121 supplies video data synchronized with the Clock Enable.
By means of a configuration in which the circuit shown in FIG. 3 is applied to each of link separation circuit 104, UNPACK circuits 106 and 107, and image adjustment circuit 111, the same Clock Enable is used in each circuit, and synchronization of each of the circuits can therefore be easily established.
However, when attempting to configure the 3G-SDI processing circuits (link separation circuit 104 and UNPACK circuits 106 and 107) that process 3G-SDI signals by FPGA (Field-Programmable Gate Arrays) in the above-described configuration, high-speed FPGA must be used to maintain timing performance.
To describe this in more concrete terms, a 3G-SDI processing circuit includes two flip-flops 131 and 132 and combinational circuit 133 such as shown in the upper portion of FIG. 5.
Each of flip-flops 131 and 132 includes clock input terminal C to which a clock is applied as input, data input terminal D to which data are applied as input, and data output terminal Q from which data are supplied as output. The data output terminal Q of flip-flop 131 is connected to the data output terminal Q of flip-flop 132 by way of combinational circuit 133.
In the above-described 3G-SDI processing circuit, a clock of 297 MHz is supplied to the clock input terminals C of each of flip-flops 131 and 132, and combinational circuit 133 operates at a clock of 297 MHz. When a circuit that operates at a high frequency of 297 MHz is made up of FPGA, the processing speed of the FPAG must be determined while taking into consideration the delay produced by the wiring in combinational circuit 133.
The price of FPGA is dependent upon the processing speed, the price increasing with the processing speed. In addition, the processing speed of the FPGA must be increased to the extent of the delay produced by the wiring in combinational circuit 133. Constituting a circuit that operates at a high frequency of 297 MHz by FPGA necessitates the use of FPGA with a high processing speed, and the cost of the device therefore increases.
In response to this problem, pipelining is implemented that improves the timing performance by dividing the processing of combinational circuit 133 between flip-flops 131 and 132 into a plurality of processes and by reducing the delay of one combinational circuit.
The lower portion of FIG. 5 shows an example of a pipeline configuration. The pipeline configuration includes three flip-flops 131, 132, and 134 and combinational circuits 133a and 133b. 
Each of flip-flops 131, 132, and 134 includes clock input terminal C to which a clock is applied as input, data input terminal D to which data are applied as input, and data output terminal Q from which data are supplied as output.
Data output terminal Q of flip-flop 131 is connected to data output terminal Q of flip-flop 134 by way of combinational circuit 133a. Data output terminal Q of flip-flop 134 is connected to data output terminal Q of flip-flop 132 by way of combinational circuit 133b. 
By means of the above-described pipeline configuration, the processing of combinational circuit 133 is divided into two portions, one portion of processing being executed by combinational circuit 133a and the other portion of processing being executed by combinational circuit 133b. Because the amount of delay produced in the wiring for each of combinational circuits 133a and 133b is less than the amount of delay produced in the wiring for combinational circuit 133 described hereinabove, FPGA of lower processing speed can be used, with the result that the cost of the device can be reduced.
In addition, in the video processing device shown in FIG. 2, a plurality of circuits (link separation circuit 104 and UNPACK circuits 106 and 107) is connected to the output line of the Clock Enable of Y/C channel separation circuit 103. The load upon the Clock Enable output line therefore increases (increased FANOUT), with the result that the amount of delay produced in the output line increases.
Accordingly, when 3G-SDI processing circuits are constituted by FPGA, the increase of FANOUT for the output line of the Clock Enable of Y/C channel separation circuit 103 must also be taken into consideration in addition to the delay produced in the wiring for combinational circuit 133 shown in FIG. 3. FPGA having high processing speed must therefore be used, resulting in an increase in the cost of the device.
In response to this problem, methods have been proposed for reducing an increase in FANOUT. A method of suppressing increase in FANOUT is described hereinbelow.
In a circuit in which four circuits 141-144 are connected in parallel to the Clock Enable output line as shown in FIG. 6, FANOUT for the output line increases, with the result that the amount of delay produced in the output line increases. A circuit such as shown in FIG. 7 is used to reduce a increase of FANOUT.
The circuit shown in FIG. 7 includes four circuits 141-144 and two flip-flops 145 and 146.
Each of flip-flops 145 and 146 includes clock input terminal C to which a clock is applied as input, input terminal D to which the Clock Enable is applied as input, and output terminal Q from which the Clock Enable is supplied as output.
Circuits 141 and 142 are connected in parallel to output terminal Q of flip-flop 145. Circuits 143 and 144 are connected in parallel to output terminal Q of flip-flop 146.
By means of the circuits shown in FIG. 7, the FANOUT for the Clock Enable output lines from output terminals Q of each of flip-flops 145 and 146 is less than in the circuit shown in FIG. 6. Accordingly, FPGA having a slower processing speed can be used to enable a reduction of the cost of the device.
A technique is described in Patent Document 1 for processing a transmission stream described by level A of 3G-SDI. A process relating to link A and link B HD-SDI is described in Patent Document 2.